The present invention generally relates to semiconductor devices, carriers for carrying semiconductor devices and methods of testing producing semiconductor devices, and more particularly to a resin encapsulated semiconductor device having a plurality of pins, a carrier for carrying such a semiconductor device and methods of testing and producing such a semiconductor device.
The number of pins of semiconductor devices has increased due to the improved integration density, and there are demands to further reduce the size of the semiconductor devices. As a result, the width and thickness of the outer leads which are arranged at an extremely fine pitch have become small, and the strength of the outer leads has become poor. For this reason, it is important that no stress is applied to the outer leads during the production stages and up to the mounting of the semiconductor device.
FIG. 1 shows an example of a conventional semiconductor device. FIG. 1(A) shows a plan view of this semiconductor device with a top part thereof omitted, and FIG. 1(B) shows a cross section of this semiconductor device along a line A--A in FIG. 1(A).
A semiconductor device 130 shown in FIG. 1 is the so-called quad flat package type in which a semiconductor chip 133 is mounted on a stage 132 which is provided at a central part of a lead frame 131. The semiconductor chip 133 and inner leads 134 of the lead frame 131 are bonded by wires 135, and are encapsulated by molding a resin 136. In addition, outer leads 137 of the lead frame 131 are respectively formed into an approximate S-shape.
For example, the packages which have been developed include those having 300 or more pins with the outer leads 137 arranged at a pitch of 0.5 mm and those having 100 or more pins with the outer leads 137 arranged at a pitch of 0.4 or 0.3 mm. Hence, the thickness of the outer leads 137 is changing from approximately 200 .mu.m to approximately 100 .mu.m.
Because the width and thickness of the outer lead 137 have become small, it is necessary to form a solder fillet on the tip end of the outer lead 137 in order to obtain a sufficiently large strength at the time of mounting the semiconductor device 130 on a substrate. Accordingly, the tip end of the outer lead 137 is usually subjected to a plating process before the mounting so as to form the solder, tin or the like on the tip end of the outer lead 137.
For example, the lead frame 131 has a construction such that the tip ends of the outer leads 137 are not connected, the plating process is carried out at a stage before the semiconductor chip 133 is mounted and only the lead frame 131 exists or, after the molding of the resin 136. The outer leads 137 are bent after this plating process.
On the other hand, if the lead frame 131 has a construction such that the tip ends of the outer leads 137 are connected, the plating process is carried out after the molding of the resin 136 and after cutting the tip ends of the outer leads 137. In this case, the outer leads 137 are also bent after this plating process.
The characteristic of the semiconductor device 130 described above is tested when forwarded by the manufacturer or received by the user. When making this test, tip ends of the outer leads 137 of the semiconductor device 130 are contacted by probes or sockets of a test equipment.
However, the width and thickness of the outer lead 137 have become small and the outer lead 137 has become weak as described above. For this reason, there is a problem in that the outer lead 137 may become deformed when contacted by the probe or socket of the test equipment in order to make the test.
In addition, when testing the semiconductor device 130, the length of the signal path from the contact of the probe or socket to the semiconductor chip 133 and including the length of the external lead 137 becomes relatively long. As a result, there is a problem in that the characteristic of the semiconductor device 130 is easily affected by the impedance of this relatively long signal path particularly when the semiconductor device 130 includes an element which operates at a high speed.
On the other hand, the plating process with respect to the outer leads 137 is carried out in a state where the tip ends of the outer leads 137 have been cut and before the outer leads 137 are bent. For this reason, there is a problem in that the outer leads 137 may become deformed after the plating process, thereby greatly deteriorating the position accuracy of the outer leads 137.
Furthermore, if the semiconductor package is handled or forwarded by the manufacturer or the user for the purpose of testing or the like after the outer leads 137 are formed and up to the time when the semiconductor device 130 is mounted, the semiconductor package is accommodated within a tray. As a result, there is a problem in that this accommodation of the semiconductor package within the tray may cause deformation of the outer leads 137.